In a FlexRay bus, data are transmitted via a plurality of elements, which each have an asymmetrical lag of signal flanks. The elements are, for example, active stars, transceivers, input buffers, and output buffers.
The asymmetrical signal lag of an element is the difference between the cycle lag of a rising signal flank and the cycle lag of a falling signal flank through the element. The causes of the asymmetrical lag may be divided into systematic and non-systematic parts. The systematic causes for an asymmetrical lag of a component are permanently predefined for the component within specified tolerance limits at a predefined operating point, for example a specific temperature or a specific supply voltage. A maximum permissible asymmetrical signal lag is fixed by the particular data transmission protocol for a data transmission. A data transmission protocol specifies, for example, that a nominal bit duration is sampled n times and the sampled value is accepted for further data processing at a predefined sampling count. The data processing includes the decoding of a serial data stream, for example. In the data transmission protocol of the FlexRay bus, for example, the nominal bit duration is sampled eight times and the sampled logical value is accepted at a sampling count of five. For the FlexRay data transmission protocol, a maximum of 37.5 ns asymmetrical lag is allowed in the transmission channel for error-free decoding. If the maximum permissible asymmetrical lag is exceeded, an incorrect bit value may be sampled. The flawed bit value is recognized, for example, via a cyclic redundancy check (CRC) and the received data are either discarded or transmitted again with additional effort in the software.
In the design of a bus system, all components causing an asymmetry in the functional chain starting from a transmitting component up to a receiving component must be taken into consideration. For this purpose, the individual asymmetry contributions are typically taken from data sheets and estimations and added up.
In integrated circuits, however, it is not possible to determine the asymmetrical lags caused by an integrated signal path, because no measuring signal may be tapped at a measuring point. An additional test signal pad for tapping a measuring signal of this type represents an unjustifiable additional technical outlay. In addition, the signal pads provided in the housing of the integrated circuit are already occupied in most cases.